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    Home»VLSI»Verilog HDL Interview Questions
    VLSI

    Verilog HDL Interview Questions

    Raju GorlaBy Raju GorlaDecember 25, 2022Updated:December 27, 2022No Comments2 Mins Read
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    Verilog HDL Interview Questions:

     

    1. Why do we need an HDL?
    2. Difference between Programming Language & Hardware Description Language
    3. What are the different types of HDLs present in the industry?
    4. Explain VHDL vs Verilog HDL
    5. Different levels of Abstraction in Verilog
    6. Explain the data types in Verilog
    7. Difference between reg and wire & default values of reg and wire
    8. Declare a 2-dimensional unpacked array
    9. Difference between $display, $strobe, $write and $monitor
    10. Difference between $finish, $stop and $reset
    11. Write a Verilog code for NAND Gate using switch-level modelling
    12. What are the different gate primitives in Verilog? Explain user-defined primitives
    13. Explain the delays in Gate Level Modelling
    14. What are the different types of operators in Verilog?
    15. Difference between == and ===
    16. Explain logical and arithmetic shifts with examples
    17. Write a Verilog code for the decoder using conditional & shift operator
    18. Explain the delays in Data Flow Modelling
    19. What are procedural blocks in Verilog and explain them
    20. Difference between the initial block and final block
    21. Explain the difference between ‘begin-end’ and ‘fork-join’
    22. Blocking vs Non-blocking assignments
    23. Explain inter and intra-assignment delays with an example
    24. Write a Verilog code RS NAND latch
    25. Write a Verilog code D-flip flop in the behavioural model (async reset with active low)
    26. Write a Verilog code for a 4-bit counter
    27. What is a parameter?
    28. Explain compiler directives
    29. Explain `timescale in Verilog
    30. Explain casex and casez statements
    31. Explain the full case and parallel case statements
    32. Difference between task and function
    33. Explain the delays in Behavioural Modelling
    34. Write a Verilog code for swapping two numbers (with & without the third variable)
    35. Write a Verilog for 4:1 MUX in gate level, dataflow & behavioural modelling
    36. Write the Verilog code for full adder using different styles
    37. Write a Verilog code for full subtractor
    38. Write a Verilog code for a 4 to 2 priority encoder using dataflow modelling
    39. Write a Verilog code for the 011 sequence (both Mealy & Moore- overlap & non-overlap)
    40. Write a Verilog code for the Mod-35 counter
    41. Write a Verilog code for the frequency divider by 3
    42. Write a Verilog code for a 4-bit up-down counter
    43. Write a Verilog code for the 1MHz clock generator
    44. Explain simulation & synthesis
    45. What are the synthesizable constructs in Verilog?
    46. What is linting?  
    47. Explain Event regions in Verilog
    48. What is structural modelling?
    49. What is meant by a generic style of coding?
    50. Explain port mapping in Verilog.

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