Verilog HDL Interview Questions:
- Why do we need an HDL?
- Difference between Programming Language & Hardware Description Language
- What are the different types of HDLs present in the industry?
- Explain VHDL vs Verilog HDL
- Different levels of Abstraction in Verilog
- Explain the data types in Verilog
- Difference between reg and wire & default values of reg and wire
- Declare a 2-dimensional unpacked array
- Difference between $display, $strobe, $write and $monitor
- Difference between $finish, $stop and $reset
- Write a Verilog code for NAND Gate using switch-level modelling
- What are the different gate primitives in Verilog? Explain user-defined primitives
- Explain the delays in Gate Level Modelling
- What are the different types of operators in Verilog?
- Difference between == and ===
- Explain logical and arithmetic shifts with examples
- Write a Verilog code for the decoder using conditional & shift operator
- Explain the delays in Data Flow Modelling
- What are procedural blocks in Verilog and explain them
- Difference between the initial block and final block
- Explain the difference between ‘begin-end’ and ‘fork-join’
- Blocking vs Non-blocking assignments
- Explain inter and intra-assignment delays with an example
- Write a Verilog code RS NAND latch
- Write a Verilog code D-flip flop in the behavioural model (async reset with active low)
- Write a Verilog code for a 4-bit counter
- What is a parameter?
- Explain compiler directives
- Explain `timescale in Verilog
- Explain casex and casez statements
- Explain the full case and parallel case statements
- Difference between task and function
- Explain the delays in Behavioural Modelling
- Write a Verilog code for swapping two numbers (with & without the third variable)
- Write a Verilog for 4:1 MUX in gate level, dataflow & behavioural modelling
- Write the Verilog code for full adder using different styles
- Write a Verilog code for full subtractor
- Write a Verilog code for a 4 to 2 priority encoder using dataflow modelling
- Write a Verilog code for the 011 sequence (both Mealy & Moore- overlap & non-overlap)
- Write a Verilog code for the Mod-35 counter
- Write a Verilog code for the frequency divider by 3
- Write a Verilog code for a 4-bit up-down counter
- Write a Verilog code for the 1MHz clock generator
- Explain simulation & synthesis
- What are the synthesizable constructs in Verilog?
- What is linting?
- Explain Event regions in Verilog
- What is structural modelling?
- What is meant by a generic style of coding?
- Explain port mapping in Verilog.